ds023 (v2.1) march 31, 2006 www.xilinx.com 1 product specification ? 2006 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? low power 3.3v 32 macrocell cpld ? 4.5 ns pin-to-pin logic delays ? system frequencies up to 213 mhz ? 32 macrocells with 750 usable gates ? available in small footprint packages - 48-ball cs bga (36 user i/o pins) - 44-pin vqfp (36 user i/o) - 44-pin plcc (36 user i/o) ? optimized for 3.3v systems - ultra-low power operation - typical standby current of 17 a at 25 c - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five layer metal eeprom process - fast zero power? (fzp) cmos technology - 3.3v pci electrical specification compatible outputs (no internal clamp diode on any input or i/o, no minimum clock input capacitance) ? advanced system features - in-system programming - input registers - predictable timing model - up to 23 available clocks per function block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per function block ? fast isp programming times ? port enable pin for dual function of jtag isp pins ? 2.7v to 3.6v supply voltage at industrial temperature range ? programmable slew rate control per macrocell ? security bit prevents unauthorized access ? refer to the coolrunner xpla3 family data sheet ( ds012 ) for architecture description description the coolrunner? xpla3 xcr3032xl device is a 3.3v, 32-macrocell cpld targeted at power sensitive designs that require leading edge programmable logic solutions. a total of two function blocks provide 750 usable gates. pin-to-pin propagation delays are as fast as 4.5 ns with a maximum system frequency of 213 mhz. totalcmos design technique for fast zero power coolrunner xpla3 cplds offer a totalcmos? solution, both in process technology and design technique. xilinx cplds employ a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and table 1 show- ing the i cc vs. frequency of our xcr3032xl totalcmos cpld (data taken with two resetable up/down, 16-bit counters at 3.3v, 25 c). 0 xcr3032xl 32 macrocell cpld ds023 (v2.1) march 31, 2006 014 product specification r figure 1: i cc vs. frequency at v cc = 3.3v, 25c 5 0 1 0 1 5 2 0 0 2 0 4 0 60 80 1 00 12 0 14 0 1 60 1 80 2 00 frequenc y (mhz ) ds023 _ 01 _ 08010 1 ty pical i cc ( ma ) table 1: i cc vs. frequency (v cc = 3.3v, 25c) frequency (mhz) 0 1 5 10 20 50 100 200 typical i cc (ma) 0.017 0.13 0.54 1.06 2.09 5.2 10.26 20.3
xcr3032xl 32 macrocell cpld 2 www.xilinx.com ds023 (v2.1) march 31, 2006 product specification r dc electrical characteristics over recommended operating conditions (1) symbol parameter test conditions typical min. max. unit v oh ( 2 ) output high voltage v cc = 3.0v to 3.6v, i oh = ?8 ma - 2.4 - v v cc = 2.7v to 3.0v, i oh = ?8 ma - 2.0 - v i oh = ?500 a - 90% v cc ( 3 ) -v v ol output low voltage i ol = 8 ma - - 0.4 v i il ( 4 ) input leakage current v in = gnd or v cc to 5.5v - ?10 10 a i ih ( 4 ) i/o high-z leakage current v in = gnd or v cc to 5.5v - ?10 10 a i ccsb ( 8 ) standby current v cc = 3.6v 24.5 - 100 a i cc dynamic current ( 5 , 6 ) f = 1 mhz - - 0.25 ma f = 50 mhz - - 7.5 ma c in input pin capacitance ( 7 ) f = 1 mhz - - 8 pf c clk clock input capacitance ( 7 ) f = 1 mhz - - 12 pf c i/o i/o pin capacitance ( 7 ) f = 1 mhz - - 10 pf notes: 1. see the coolrunner xpla3 family data sheet ( ds012 ) for recommended operating conditions 2. see figure 2 for output drive characteristics of the xpla3 family. 3. this parameter guaranteed by design and characterization, not by testing. 4. typical leakage current is less than 1 a. 5. see ta b l e 1 , figure 1 for typical values. 6. this parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 7. typical values, not tested. 8. typical value at 70 c. figure 2: typical i/v curve for the coolrunner xpla3 family, 25c 0 0 1 0 2 0 30 4 0 50 60 7 0 80 90 1 00 0 . 5 1 1. 5 2 2. 5 3 3 . 5 4 4. 5 5 volt s i o l ( 3.3v ) i o h ( 3.3v ) i o h ( 2.7v ) ma ds012 _ 10 _ 03180 2
xcr3032xl 32 macrocell cpld ds023 (v2.1) march 31, 2006 www.xilinx.com 3 product specification r ac electrical characteristics over recommended operating conditions (1,2) symbol parameter -5 -7 -10 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) 4.5 - 7.0 - 9.1 ns t pd2 propagation delay time (or array) (3) 5.0 - 7.5 - 10.0 ns t co clock to output (global synchronous pin clock) 3.5 5.0 - 6.5 ns t suf setup time (fast input register) 2.5 - 3.0 - 3.0 - ns t su1 (4) setup time (single p-term) 3.0 - 4.3 - 5.4 - ns t su2 setup time (or array) 3.5 - 4.8 - 6.3 - ns t h (4) hold time 0 - 0 - 0 - ns t wlh (4) global clock pulse width (high or low) 2.5 - 3.0 - 4.0 - ns t plh (4) p-term clock pulse width 4.0 - 5.0 - 6.0 - ns t aprpw asynchronous preset/reset pulse width (high or low) 4.0 - 5.0 - 6.0 - ns t r (4) input rise time - 20 - 20 - 20 ns t l (4) input fall time - 20 - 20 - 20 ns f system (4) maximum system frequency - 213 - 119 - 95 mhz t config (4) configuration time (5) -30-30-30 s t init (4) isp initialization time - 30 - 30 - 30 s t poe (4) p-term oe to output enabled - 7.2 - 9.3 - 11.2 ns t pod (4) p-term oe to output disabled (6) - 7.2 - 9.3 - 11.2 ns t pco (4) p-term clock to output - 6.0 - 8.3 - 10.7 ns t pao (4) p-term set/reset to output valid - 6.5 - 9.3 - 11.2 ns notes: 1. specifications measured with one output switching. 2. see coolrunner xpla3 family data sheet ( ds012 ) for recommended operating conditions. 3. see figure 4 for derating. 4. these parameters guaranteed by design and/or characterization, not testing. 5. typical current draw during configuration is 3 ma at 3.6v. 6. output c l = 5 pf.
xcr3032xl 32 macrocell cpld 4 www.xilinx.com ds023 (v2.1) march 31, 2006 product specification r internal timing parameters (1,2) symbol parameter -5 -7 -10 unit min. max. min. max. min. max. buffer delays t in input buffer delay - 0.7 - 1.6 - 2.2 ns t fin fast input buffer delay - 2.2 - 3.0 - 3.1 ns t gck global clock buffer delay - 0.7 - 1.0 - 1.3 ns t out output buffer delay - 1.8 - 2.7 - 3.6 ns t en output buffer enable/disable delay - 4.5 - 5.0 - 5.7 ns internal register, product term, and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 1.0 - 1.0 - 1.2 - ns t hi register hold time 0.3 - 0.5 - 0.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to output delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.0 - 2.3 - 2.1 ns t rai register async. recovery - 3.5 - 5.0 - 6.0 ns t ptck product term clock delay - 2.5 - 2.7 - 3.3 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.2 - 4.2 ns feedback delays t f zia delay - 0.2 - 2.9 - 3.5 ns time adders t logi3 fold-back nand delay - 2.0 - 2.5 - 3.0 ns t uda universal delay - 1.2 - 2.0 - 2.5 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns notes: 1. these parameters guaranteed by design and characterization, not testing. 2. see the coolrunner xpla3 family data sheet ( ds012 ) for timing model.
xcr3032xl 32 macrocell cpld ds023 (v2.1) march 31, 2006 www.xilinx.com 5 product specification r switching characteristics figure 3: ac load circuit ds023_03_102401 component values r1 390 r2 390 c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed v cc v out v in c1 r1 r2 s1 s2 note: for t pod , c1 = 5 pf. delay measured at output level of v ol + 300 mv, v oh ? 300 mv. figure 4: derating curve for t pd2 3 . 0 3 . 5 4. 0 4. 5 1 2 4 8 1 6 d s023 _ 05 _ 06110 1 out p ut s t pd ( ns ) figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns ds023_06_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
xcr3032xl 32 macrocell cpld 6 www.xilinx.com ds023 (v2.1) march 31, 2006 product specification r pin descriptions table 2: xcr3032xl user i/o pins pc44 vq44 cs48 total user i/o pins 36 36 36 table 3: xcr3032xl i/o pins function block macrocell pc44 vq44 cs48 11442a2 12543a1 13644c4 147 (1) 1 (1) b1 (1) 1582c2 1693c1 17115d3 18126d1 1913 (1) 7 (1) d2 (1) 110148e1 1111610f1 1121711g1 1131812e4 1 141913f2 1152014g2 1 162115f3 2 1 41 35 c5 2 2 40 34 a6 2 3 39 33 b6 2438 (1) 32 (1) b7 (1) 2 5 37 31 d4 2 6 36 30 c6 2 7 34 28 d6 2 8 33 27 d7 2932 (1) 26 (1) e5 (1) 2103125e7 2112923f7 2122822g7 2132721g6 2 142620f5 2152519g5 2 162418f4 notes: 1. jtag pins table 4: xcr3032xl global, jtag, port enable, power, and no connect pins pin type pc44 vq44 cs48 in0 / clk0 2 40 a3 in1 / clk1 1 39 b4 in2 / clk2 44 38 a4 in3 / clk3 43 37 b5 tck 32 26 e5 tdi 7 1 b1 tdo 38 32 b7 tms 13 7 d2 port_en 10 (1) 4 (1) c3 (1) v cc 3, 15, 23, 35 9, 17, 29, 41 b3, c7, e2, g4 gnd 22, 30, 42 16, 24, 36 a5, e3, e6 no connects - - a7, b2, f6, g3 notes: 1. port enable is brought high to enable jtag pins when jtag pins are used as i/o. see family data sheet ( ds012) for full explanation. table 3: xcr3032xl i/o pins function block macrocell pc44 vq44 cs48
xcr3032xl 32 macrocell cpld ds023 (v2.1) march 31, 2006 www.xilinx.com 7 product specification r device part marking ordering combination information device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1) xcr3032xl-5pc44c 5 ns pc44 44 plastic leaded chip carrier (plcc) c xcr3032xl-5pcg44c 5 ns pcg44 44 plastic leaded chip carrier (plcc); pb-free c xcr3032xl-5vq44c 5 ns vq44 44 very thin quad flat pack (vqfp) c xcr3032xl-5vqg44c 5 ns vqg44 44 very thin quad flat pack (vqfp); pb-free c xcr3032xl-5cs48c 5 ns cs48 48 chip scale package (csp) c xcr3032xl-5csg48c 5 ns csg48 48 chip scale package (csp); pb-free c xcr3032xl-7pc44c 7.5 ns pc44 44 plastic leaded chip carrier (plcc) c xcr3032xl-7pcg44c 7.5 ns pcg44 44 plastic leaded chip carrier (plcc); pb-free c xcr3032xl-7vq44c 7.5 ns vq44 44 very thin quad flat pack (vqfp) c xcr3032xl-7vqg44c 7.5 ns vqg44 44 very thin quad flat pack (vqfp); pb-free c xcr3032xl-7cs48c 7.5 ns cs48 48 chip scale package (csp) c xcr3032xl-7csg48c 7.5 ns csg48 48 chip scale package (csp); pb-free c xcr3032xl-7pc44i 7.5 ns pc44 44 plastic leaded chip carrier (plcc) i xcr3032xl-7pcg44i 7.5 ns pcg44 44 plastic leaded chip carrier (plcc); pb-free i xcr3032xl-7vq44i 7.5 ns vq44 44 very thin quad flat pack (vqfp) i xcr3032xl-7vqg44i 7.5 ns vqg44 44 very thin quad flat pack (vqfp); pb-free i xcr3032xl-7cs48i 7.5 ns cs48 48 chip scale package (csp) i xcrxxxxxl tq144 7c device type package speed operating range this line not related to device part number sample package with part marking. r 1 notes: 1. due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. part marking on chip scale packages by line: line 1 = x (xilinx logo), then truncated part number (no xc), i.e., 3064xl. line 2 = not related to device part number. line 3 = not related to device part number. line 4 = package code, speed, operating temperature, three digits not related to device part number. package codes; c1 = cs48, c2 = csg48.
xcr3032xl 32 macrocell cpld 8 www.xilinx.com ds023 (v2.1) march 31, 2006 product specification r xcr3032xl-7csg48i 7.5 ns csg48 48 chip scale package (csp); pb-free i xcr3032xl-10pc44c 10 ns pc44 44 plastic leaded chip carrier (plcc) c xcr3032xl-10pcg44c 10 ns pcg44 44 plastic leaded chip carrier (plcc); pb-free c xcr3032xl-10vq44c 10 ns vq44 44 very thin quad flat pack (vqfp) c xcr3032xl-10vqg44c 10 ns vqg44 44 very thin quad flat pack (vqfp); pb- free c xcr3032xl-10cs48c 10 ns cs48 48 chip scale package (csp) c xcr3032xl-10csg48c 10 ns csg48 48 chip scale package (csp); pb-free c xcr3032xl-10pc44i 10 ns pc44 44 plastic leaded chip carrier (plcc) i XCR3032XL-10PCG44I 10 ns pcg44 44 plastic leaded chip carrier (plcc); pb-free i xcr3032xl-10vq44i 10 ns vq44 44 very thin quad flat pack (vqfp) i xcr3032xl-10vqg44i 10 ns vqg44 44 very thin quad flat pack (vqfp); pb-free i xcr3032xl-10cs48i 10 ns cs48 48 chip scale package (csp) i xcr3032xl-10csg48i 10 ns csg48 48 chip scale package (csp); pb-free i notes: 1. c = commercial: t a = 0 to +70c; i = industrial: t a = ?40 to +85c ordering combination information (continued) device ordering and part marking number speed (pin-to-pin delay) pkg. symbol no. of pins package type operating range (1)
xcr3032xl 32 macrocell cpld ds023 (v2.1) march 31, 2006 www.xilinx.com 9 product specification r warranty disclaimer these products are subject to the terms of the xilinx limited warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of the products in an application or environment that is not within the specifications stated on the then-current xilinx data sheet for the produc ts. products are not designed to be fail-safe and are not warranted for use in applications th at pose a risk of physical harm or loss of life. use of products in such applications is fully at the risk of customer subject to applicable laws and regulations. additional information coolrunner xpla3 data sheets and application notes device packages device package user guide revision history the following table shows the revision history for this document. date version revision 11/18/00 1.0 initial xilinx release. 02/05/01 1.1 removed timing model. 04/11/01 1.2 update tsuf spec to meet umc characterization data. added icc vs. freq. numbers, ta b le 1 and updated figure 1 . added typical i/v curve, figure 2 ; added ta b l e 2 : total user i/o; changed v oh spec. 04/19/01 1.3 updated typical i/v curve, figure 2 : added voltage levels. 08/27/01 1.4 changed from advance to preliminary; updated dc electrical characteristics; ac electrical characteristics; internal timing parameters; added derating curve; added -10 industrial packages. added 200 mhz to figure 1 and ta b le 1 . changed -5 f system to 200 mhz, -5 t f to 0.5 ns. 01/08/02 1.5 updated t hi spec to correct a typo. added single p-term setup time (t su1 ) to ac table, renamed t su to t su2 for setup time through the or array. updated ac load circuit diagram to more closely resemble true test conditions, added note for t pod delay measurement.updated note 5 in ac characteristics table lowering typical current draw during configuration. 01/06/03 1.6 added voltage and temperature to figure 2 . increased -5 t pco to 6.0 (from 5.5 ns) by adding t ptck parameter to internal timing model. increased -5 f max . updated ordering information format. 07/15/03 1.7 updated device part marking. updated test conditions for i il and i ih . 08/21/03 1.8 updated package device marking pin 1 orientation. 02/13/04 1.9 add solder temperature specification. add links to data sheets, application notes and packages. 04/08/05 2.0 added i ccsb typical and t aprpw specifications. removed t sol specification. added note about pb-free packages. 03/31/06 2.1 added warranty disclaimer; added pb-free ordering information.
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